Workshop 08- APMM

International Workshop on New Algorithms and Programming Models for the Manycore Era

(APMM 2011)

Call for Papers

As part of

The 2011 International Conference on High Performance Computing & Simulation

(HPCS 2011)

http://hpcs11.cisedu.info/

In Conjunction With

The International Wireless Communications and Mobile Computing Conference (IWCMC 2011)

July 4 – 8, 2011

Istanbul, Turkey

(Submission Deadline: February 28, 2011)

SCOPE AND OBJECTIVE

With multi- and many-core based systems, performance increase on the microprocessor side will continue according to Moore's Law, at least in the near future. However, the already existing performance limitations due to slow memory access are expected to get worse with multiple cores on a chip, and complex hierarchies of cache memory will make it hard for users to fully exploit the theoretically available performance. In addition, the increasingly hybrid and hierarchical design of compute clusters and high-end supercomputers, as well as the use of accelerator components (Cell BE or GPGPUs, e.g.) add further challenges to efficient programming in HPC applications.

Therefore, compute and data intensive tasks can only benefit from the hardware’s full potential, if both processor and architecture features are taken into account at all stages – from the early algorithmic design, via appropriate programming models, up to the final implementation.

Our workshop will address all aspects related to these issues, including, but not limited to:

• Hardware-aware, compute- and memory-intensive simulations of real-world problems in computational science and engineering (for example, from applications in electrical, mechanical, civil, or medical engineering).

• Manycore-aware approaches for large-scale parallel simulations in both implementation and algorithm design, including scalability studies.

• Parallelisation on HPC platforms; esp. platforms with hierarchical communication layout, multi-/many-core platforms, NUMA architectures, or accelerator components (Cell BE, GPU, FPGA).

• Parallelisation with appropriate programming models and tool support for multi-core and hybrid platforms.

• Software engineering, code optimisation, and code generation strategies for parallel systems with multi-core processors.

• Tools for performance and cache behavior analysis (including cache simulation) for parallel systems with multi-core processors.

Paper Submission, Registration, and Publication

You are invited to submit original and unpublished research works on one of the above topics, or on closely related topics in HPC and simulation. Please submit a PDF copy of your full manuscript, not to exceed 7 double-column IEEE formatted pages, and include up to 6 keywords and an abstract of no more than 450 words. Additional pages will be charged additional fee. Each paper will receive a minimum of three reviews. At least one of the authors of each accepted paper will have to register and attend the HPCS 2011 conference for presenting the paper at the workshop. Accepted papers will be published in the conference proceedings which will be available at the time of the meeting. Papers should be submitted as PDF files only, and via email to Michael.Bader@ipvs.uni-stuttgart.de and Josef.Weidendorfer@cs.tum.edu.

If you have any questions about paper submission or the workshop, please contact the organizers.

Important Dates:

• Full Paper Submission Deadline: February 28, 2011

• Notification of Acceptance: March 24, 2011

• Extended Registration & Camera-Ready Manuscripts Due: April 29, 2011

• Conference Date: July 4-8, 2011