Workshop 04- MPSoC
Workshop on Multiprocessor Systems on (Programmable) Chips
(MPSoC 2011)
Call for Papers
As part of
The 2011 International Conference on High Performance Computing & Simulation (HPCS 2011)
In Conjunction With
The International Wireless Communications and Mobile Computing Conference (IWCMC 2011)
July 4 – 8, 2011
Istanbul, Turkey
(Submission Deadline: March 6, 2011)
SCOPE AND OBJECTIVE
Moore’s law continues to track the number of transistors that can be fabricated within a single FPGA, and manufacturers are now shipping components that can host complete multiprocessor systems on a reconfigurable programmable chip (MPSoPC). Based on this new capability FPGA manufactures are now challenging systems designers to view the processor in place of the transistor as the least separable design unit. Thus FPGA’s can now be viewed as yet one more technology platform within the multiprocessor systems on chip manycore era. Even though specific technologies may vary, system designers across the embedded systems, general purpose internet computing systems, and high performance systems domains are now facing common challenges associated with multiprocessor systems on (programmable) chip design. Common architecture issues include architecture heterogeneity, cache and memory hierarchies, and high performance interconnect networks. Common software issues include low latency and scalable operating systems, new coordination layers, and scalable programming models capable of seamlessly abstracting large numbers of potentially heterogeneous cores on a single chip into a single unified virtual platform. The aim of this workshop is to provide a forum for idea exchange and foster technology transfer between the reconfigurable, embedded systems, and general purpose communities that will foster synergistic resolution of these and other challenging issues.
The Workshop topics include (but are not limited to) the following:
OS Development for Reconfigurable and Many-core Systems
Reconfigurable/Embedded Network-on-Chip
Memory Hierarchies for Single Chip Parallel Architectures
Reconfigurable/Embedded System Security
Resilience in Embedded Systems
Programmability and Productivity
Performance Analysis, Prediction, and Parallel System Emulation
Languages, Libraries and Compilers for Reconfigurable and Manycore Computing
High-Performance Reconfigurable Computing Applications
HPC and Large Scale Parallel System Emulation
PAPER SUBMISSIONS
You are invited to submit original and unpublished research works on above and other topics related to multiprocessor systems on programmable chips. Submitted papers must not have been published or simultaneously submitted elsewhere. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and authors email addresses. Please, indicate clearly the corresponding author and include up to 6 keywords from the above list of topics and an abstract of no more than 450 words. The full manuscript should be at most 7 pages using the two-column IEEE format. Additional pages will be charged additional fee. Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments. Submit a PDF copy of your full manuscript via email to the Workshop organizers at dandrews@uark.edu and mqhuang@uark.edu.
Only PDF files will be accepted. Each paper will receive a minimum of three reviews. Papers will be selected based on their originality, contributions, relevance, technical clarity and presentation. Authors of accepted papers must guarantee that their papers will be registered and presented at the workshop. Accepted papers will be published in the conference proceedings which will be made available at the time of the meeting.
If you have any questions about paper submission or the workshop, please contact the organizers.
Important Dates:
Full Paper Submission Deadline: March 6, 2011
Notification of Acceptance: March 27, 2011
Extended Registration & Camera-Ready Manuscripts Due: April 25, 2011
Conference Date: July 4-8, 2011
WORKSHOP ORGANIZERS
Prof. Miaoqing Huang and Prof. David Andrews
University of Arkansas, USA
URLs: http://www.csce.uark.edu/~mqhuang/ , http://www.csce.uark.edu/~dandrews/
Phone: (479) 575-7578
Emails: mqhuang@uark.edu, dandrews@uark.edu
International Program Committee:
All submitted papers will be rigorously reviewed by the workshop technical program committee members following similar criteria used in HPCS 2011.
Jason Agron, Intel, USA
David Andrews, University of Arkansas, AR, USA
Jason Bakos, University of South Carolina, SC, USA
Christophe Bobda, University of Arkansas, AR, USA
Esam El-Araby, The Catholic University of America, USA
Miaoqing Huang, University of Arkansas, AR, USA
Vikram Narayana, The George Washington University, D.C., USA
Christian Plessl, University of Paderborn, Germany
Ron Sass, University of North Carolina at Charlotte, NC, USA
TBA
For information or questions about Conference's paper submission, tutorials, posters, workshops, special sessions, exhibits, demos, panels and forums organization, doctoral colloquium, and any other information about the conference location, registration, paper formatting, etc., please consult the Conference’s web site at URL: http://hpcs11.cisedu.info/ or contact one of the Conference's organizers. If you have any questions about the HPCS 2011 conference paper submission, please contact Conference Program Chair: Waleed W. Smari, Voice: +1 (937) 681-0098, Email: smari@arys.org.